Intel and Metaswitch lights-up the 5G Core with a 500 Gbps Cloud Native UPF
In recent testing, certified by Intel® engineers, Metaswitch has demonstrated the Metaswitch Fusion Core® User Plane Function (UPF) delivering superior 5G packet processing throughput when deployed within containers on standard server platforms leveraging Intel Xeon® Gold 6254 scalable processors. Employing Internet MIX (IMIX) traffic profiles and using a total of 34 CPU cores, a single-server UPF achieved a packet throughput of over 500 Gbps using a benchmark mobile data pipeline.
A long-time Intel Network Builders partner in the area of data plane acceleration, Metaswitch has developed a complete cloud-native 5G core solution featuring a pure software UPF that meets the performance and resource efficiency needs of high-throughput 5G networks. To fulfill the UPF functionality, the Metaswitch solution is built to run on commercial off-the-shelf (COTS) servers powered by Intel Xeon processors. It features an industry-leading, high-performance, forwarding engine and a unique distributed state implementation for resiliency and granular scalability cloud infrastructures. This is achieved on an extraordinarily small processing footprint at a very low price point, which is increasingly important for platforms deployed within MEC environments.
The test comprised 100,000 sessions from 160 simulated gNBs with a total of 10,000 Access Control Lists (ACLs) provisioned. A complete UPF packet processing pipeline was utilized with full GPRS Tunneling Protocol (GTP) encapsulation/decapsulation plus session-based policing and metering. Two asymmetric traffic profiles were used, with differing ratios of uplink to downlink traffic.
Metaswitch Fusion Core Performance Testing Results.
Typically the domain of customized application-specific integrated circuits (ASICs) and network processor (NPU) hardware in dedicated appliances, the 5G UPF is a pure software-based packet-forwarding platform. It must implement rapid encoding and decoding of tunneled IP payloads, applying complex pipelines and enforcing stringent Quality of Service (QoS) metrics while consuming as few compute resources as possible.
While the open-source Data Plane Development Kit (DPDK) has helped accelerate packet processing within COTS servers, such polled zero-copy direct memory access techniques cannot, on their own, provide the levels of price/performance required of core network routing functions with numerous forwarding rules and multi-layer encapsulation.
The Composable Network Application Processor (CNAP) is a flexible and powerful software packet processing engine that Metaswitch developed to provide the foundation for virtualized network functions that handle data plane traffic. With a unique combination of programmability and performance, CNAP implements a packet-processing pipeline with match-action classifiers that allow lookups on multiple elements of the packet header in a single operation. With careful design of the packet pipeline, this allows multiple logical operations to be collapsed into a single match-action step.
CNAP makes the best possible use of instruction and data caches in Intel® x86 architecture CPUs to maximize efficiency. In addition to processing packets in batches, CNAP leverages explicit pre-fetch instructions and process interleaving to avoid cache stalls while ensuring that all match-action instructions, packet header data, and lookup table data are in-cache for the fastest possible execution. The pipeline is described by a gRPC API with P4-like semantics and applied using a series of API calls to the CNAP engine. This allows complete flexibility in configuring the UPF to implement new data plane protocols or tunneling techniques without the typically long development cycle. A fully containerized Metaswitch UPF can be deployed on a minimum of three processor cores, allocated respectively to management and control plus an uplink and downlink packet processing engine.
Simon is the Director of Technical Marketing and a man of few words.